1. Field of the Invention
The present invention relates to a semiconductor memory having a plurality of cell arrays and a global bit line for common use for the cell arrays.
2. Description of the Related Art
In a semiconductor memory such as a SRAM, a bit line connected to memory cells generally has been elongated in accordance with an increase in memory capacity. The increase in the length of the bit line increases load capacitance of the bit line, resulting in a longer access time. In order to prevent the increase in the access time due to the load capacitance of the bit line, proposed is a bit line having a hierarchical structure (for example, disclosed in Japanese Unexamined Patent Application Publication No. 2005-166098). In this art, a plurality of cell arrays having independent bit lines are formed, and a global bit line for common use for these cell arrays is arranged.
Meanwhile, in some system LSI in which a logic circuit and a memory circuit (semiconductor memory) are mounted on one chip, a memory capacity can be set according to user specification. In a system LSI of this kind, the semiconductor memory is formed as a RAM macro by using a compiler which is one of design tools of the system LSI. For example, the compiler calculates the number of word lines according to the memory capacity to allocate addresses to the respective word lines.
The compiler has, as a library, a basic cell array (complete cell array) having a predetermined memory capacity. The compiler calculates the number of the basic cell arrays to be formed on a chip according to a memory capacity needed by a user. When the memory capacity is not an integral multiple of the capacity of the basic cell array, the compiler forms an incomplete cell array smaller than the basic cell array. In typical layout design, the basic cell array is disposed on a closer side to an I/O circuit, while the incomplete cell array is disposed on the most distant side from the I/O circuit. Bit lines of the respective cell arrays and a global bit line for common use for the cell arrays are wired in a direction of the cell array arrangement.
Load capacitance of the global bit line increases as the global bit line increases in length. Therefore, when the load capacitance of the global bit line is large due to the long global bit line, charge/discharge current of the global bit line becomes large at an access time of the semiconductor memory. This results in an increase in power consumption and an increase in the access time. However, no consideration has been given heretofore to the length of the global bit line for arranging the cell arrays.